1. Field of the Invention
The present invention relates to a semiconductor memory device and a testing method thereof, and more specifically to a dynamic semiconductor memory (DRAM) having refresh modes such as a self refresh and an auto-refresh in particular, which has a control circuit for carrying out a function test of-an internal counter for refresh (refresh counter) built in for generating a row address for a refreshing operation, and a measurement of a counter cycle (refresh interval) at the time of refresh, and a testing method for the DRAM.
2. Description of the Related Art
In many cases, the inspection of DRAM devices, which is carried out during the course of the production or after the product is completed, includes an operation test of its refresh counter (counter test). The refresh counter is incremented the row address so as to restore (refresh) the charge on a memory cell DRAM. The refresh operation can be generally divided into an auto-refresh and a self-refresh. In the auto-refresh operation, the refresh cycle is controlled by a signal from outside, whereas in the self-refresh mode, the refresh cycle is controlled by an internal signal. The self-refresh operation is used at the time of the battery back-up of the DRAM device, and the standby of the device.
In a conventional DRAM device, there is provided a test circuit exclusively for testing whether or not the switching of address is appropriately carried out at the time of a refresh operation, by incrementing an output signal (row address) of the refresh counter. Such an exclusive test circuit occupies a large area in the device and causes an increase in the production cost.
The operation test for the refresh counter can be replaced of an operation test of the self refresh mode of the DRAM, even without the above-described exclusive test circuit. First, in the normal operation mode, data "1" (cell level="H") is written in a memory cell of the DRAM. Next, the operation is switched into the self-refresh mode. Then, the operation waits for a time period sufficiently longer than the pause time of the memory cell which is the object of the measurement, that is, the self-refresh operation is being continued. Next, the data of the memory cell is read out and examined as to whether or not the data is the same as the data written in advance (whether or not the data is broken). The operation test of the self-refresh mode requires a time period sufficiently longer than the pause time of the memory cell as described above. Such a time period is usually longer than the refresh time period of the DRAM, and is as long as a few seconds in total. Thus, the conventional device involves an increase in test requiring time, and causes an increase in test cost and, accordingly a production cost.
Meanwhile, in a self-refresh mode, the cycle of the refresh counter is determined automatically by the internal clock, and therefore the accurate cycle of the counter cannot be known from outside. For example, in some of the PSRAMs (pseudo-static RAMs) having self-refresh modes, a test circuit exclusively for testing a pulse output from a particular input/output pins in accordance with the counter cycle, is provided so as to measure the cycle of the refresh counter at the time of the self-refresh operation, that is, refresh interval. However, if such an exclusive test circuit for measuring a refresh interval is provided, the size of a chip is increased, causing an increase in chip cost and production cost. Further, a chip including the exclusive test circuit, has a structure in which an excessive load is inevitably applied to a particular input/output pin, and therefore a high-speed operation device, especially, such as a recent synchronous type DRAM is adversely affected in terms of output waveform.